The present invention is directed to a method for the electrical insulation of a function element, particularly a transistor, on a semiconductor component on which further function elements are integrated.
Hetero-components on semiconductor material partly contain highly conductive semiconductor layers that cover the entire semiconductor wafer in a thickness of 1 through 2.5 .mu.m; individual function elements of such a component must therefore be electrically insulated from the remaining parts of the component. Various methods have been previously disclosed for forming this insulation.
Insulation regions can be produced in the semiconductor material by deep insulation implantation, for example with B.sup.++ given acceleration voltages in the MV range, or with H.sup.+, O.sup.+. Disadvantages of these methods are that they are fundamentally not employable for highly doped layers, so that a combination of this implantation with re-etching of the semiconductor material is required. Moreover, the implantation requires complex equipment that is not easily available. Extremely narrow function elements etched as mesas cannot be insulated with this method because of the lateral scatter of the implantation. When the width of the mesa falls below twice the depth of the mesa, the upper parts of the mesa are electrically insulated from the lower parts thereof, i.e., are cut off by the implantation. A boron implantation is temperature-stable up to only approximately 450.degree. C.
Electrically separating every individual function element on the semiconductor component from the others by separate etching of a mesa, as disclosed, for example, in the publication by S. J. Prasad et al., "An Implant-Free AlGaAs/GaAs HBT IC Technology Incorporating 1.4 THz Schottky Diodes" in IEEE 1991 Bipolar Circuits and Technology Meeting Jul. 3, Minneapolis, Minn., has the disadvantage that problems derive in the phototechnique employed and in the coverage of the steps with metallizations. A further possibility of insulation is established by etching insulating trenches that are subsequently filled with a dielectric (similar to the oxide insulation processes of bipolar silicon technology). For example, such a method is disclosed in the publication by G. Packeiser, H. Tews, P. Zwicknagl, "High Frequency AlGaAs/GaAs Hetero-Junction Bipolar Transistors: The Role of MOVPE", Journal of Crystal Growth 107, 883-892 (1991).
Another method involves etching mesas and subsequently filling of the regions situated between these mesas with polyimide. The employment of polyimide as a planarizing material is disclosed, for example, in L. G. Shantharama, H. Schumacher, J. R. Hayes, Z. Bhat, R. Esagui, M. Koza, "Fully Self-Aligned Microwave InP/GaInAs Single Heterojunction Bipolar Transistors", Electronic Letters 25, 127 through 128 (1989). Some of the disadvantages of using polyimide are surface roughness, premature aging due to high absorption of moisture, shrinkage and limited temperature stability of the polyimide.
A method for planarizing the surface of a semiconductor component with a dielectric is disclosed, for example, by EP 0 416 165 A1.